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Size: 345378 |
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Description: 这是arm jtag仿真器的电路图，速度快，带有cpld。-This is the circuit diagram of arm jtag simulator,with high speed,cpld attatched.
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Size: 1758 |
Author: 陈坚胜 |
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Description: JTAG CPLD实现源代码，比用简单并口调试器快5倍以上。
以前总觉得简单的并口jtag板速度太慢，特别是调试bootloader的时候，简直难以忍受。最近没什么事情，于是补习了几天vhdl，用cpld实现了一个快速的jtag转换板。cpld用epm7128stc100-15，晶振20兆，tck频率5兆。用sjf2410作测试，以前写50k的文件用时5分钟，现在则是50秒左右。tck的频率还可以加倍，但是不太稳定，而且速度的瓶颈已经不在tck这里，而在通讯上面了。
-JTAG CPLD source code than the simple parallel debugger five times faster. Before feel simple parallel port JTAG board is too slow, especially when debugging Bootloader, simply intolerable. No matter recently, so VHDL tutorial for a few days, with cpld to achieve a rapid conversion of JTAG board. Cpld with epm7128stc100-15, 20 Katherine crystal, the frequency tck 5 trillion. Sjf2410 used for testing, before the document was made with 50k at 5 minutes, now it is about 50 seconds. Tck frequencies can also doubled, but not too stable, but the rate has not tck bottleneck here, and in the above communications.
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Size: 2023 |
Author: 李伟 |
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Description: XilinxJTAG.rar
xilinx CPLD,FPGA的JTAG口使用说明.-XilinxJTAG.rar Xilinx CPLD, FPGA JTAG I use.
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Size: 430872 |
Author: 何 |
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Description: turbo jtag CPLD source code
use altera EPM7128S
-turbo jtag CPLD source code use altera EPM7 128S
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Size: 2105 |
Author: z8848 |
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Description: ARM和CPLD的JTAG的原理图，以及PCB图，为公司做的，顺便发出来，有需要的可以下栽
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Size: 608729 |
Author: 张金辉 |
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Description: CPLD ARM等JTAG下载线,ISP编程使用，Protell99格式
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Size: 181326 |
Author: 徐松涛 |
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Description: 本人自己制作的JTAG下载线，只用了一片244,可以支持ARM9、Cortex™ -M3、CPLD、FPGA、89S52等。目前这些已经测试通过。性能稳定。但是注意74LS244和74HC244在性能上可能会有些区别
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Size: 9513 |
Author: 刘意 |
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Description: This is LPT JTAG programmer for Xilinx FPGA/CPLD chips and for ARM-core microcontrollers.
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Size: 90112 |
Author: Entoja |
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Description:
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Size: 477184 |
Author: 陶宇 |
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Description: FPGA或者CPLD通过JTAG接口口对FLASH进行读写的资料。非常有用
-FPGA or CPLD through the JTAG interface port on the FLASH read and write information. Very useful
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Size: 305152 |
Author: lihoulian |
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Description:
JTAG_CPLD_project source VHDL code ，适用于开发JTAG接口。此工程使用Altera EPM570 MAX II CPLD，包含硬件和软件描述。-JTAG_CPLD_project source VHDL code, suitable for the development of the JTAG interface. This project using the Altera EPM570 MAX II CPLD, includes hardware and software description.
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Size: 1273856 |
Author: Jeff_Cai |
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Description: OpenOCD provides on-chip programming and debugging support with a
layered architecture of JTAG interface and TAP support including:
- (X)SVF playback to faciliate automated boundary scan and FPGA/CPLD
programming
- debug target support (e.g. ARM, MIPS): single-stepping,
breakpoints/watchpoints, gprof profiling, etc
- flash chip drivers (e.g. CFI, NAND, internal flash)
- embedded TCL interpreter for easy scripting.-OpenOCD provides on-chip programming and debugging support with a
layered architecture of JTAG interface and TAP support including:
- (X)SVF playback to faciliate automated boundary scan and FPGA/CPLD
programming
- debug target support (e.g. ARM, MIPS): single-stepping,
breakpoints/watchpoints, gprof profiling, etc
- flash chip drivers (e.g. CFI, NAND, internal flash)
- embedded TCL interpreter for easy scripting.
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Size: 5614592 |
Author: TeddyBear |
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Description: 可控加减计数器，带灯显示，总共是四个灯，一个进位或者借位灯，另外三个加减控制(Add and subtract counter, with light display)
Platform: |
Size: 198656 |
Author: 筱筱_asd
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